Magnetization Dynamics, Bennett Clocking and Associated Energy Dissipation in Multiferroic Logic

It has been recently shown that multiferroic logic - where logic bits are encoded in the magnetization orientation of a nanoscale magnetostrictive layer elastically coupled to a piezoelectric layer - can be Bennett clocked with small electrostatic potentials of few tens of mV applied to the piezoelectric layer. The potential generates stress in the magnetostrictive layer and rotates its magnetization by a large angle to carry out Bennett clocking. This method of clocking is far more energy-efficient than using spin transfer torque. In order to assess if such a clocking scheme can be also reasonably fast, we have studied the magnetization dynamics of a multiferroic logic array with nearest neighbor dipole coupling using the Landau-Lifshitz-Gilbert (LLG) equation. We find that switching delays of ~ 3 ns (clock rates of 0.33 GHz) can be achieved with proper design provided we clock non-adiabatically and dissipate ~48,000 kT (at room temperature) of energy per clock cycle per bit flip in the clocking circuit. This dissipation far exceeds the energy barrier separating the two logic states, which we assumed to be 32 kT to yield a bit error probability of . Had we used spin transfer torque to switch with the same ~ 3 ns delay, the energy dissipation would have been much larger (~ $6 \times 106$ kT). This shows that spin transfer torque, widely used in magnetic random access memory, is an inefficient way to switch a magnet, and multiferroic logic clocked with voltage-induced stress is a superior nanomagnetic logic scheme

Fault tolerant architectures for superconducting qubits

In this short review, I draw attention to new developments in the theory of fault tolerance in quantum computation that may give concrete direction to future work in the development of superconducting qubit systems. The basics of quantum error correction codes, which I will briefly review, have not significantly changed since their introduction fifteen years ago. But an interesting picture has emerged of an efficient use of these codes that may put fault tolerant operation within reach. It is now understood that two dimensional surface codes, close relatives of the original toric code of Kitaev, can be adapted to effectively perform logical gate operations in a very simple planar architecture, with error thresholds for fault tolerant operation simulated to be 0.75%. This architecture uses topological ideas in its functioning, but it is not 'topological quantum computation' -- there are no non-abelian anyons in sight. I offer some speculations on the crucial pieces of superconducting hardware that could be demonstrated in the next couple of years that would be clear stepping stones towards this surface-code architecture.Comment: 28 pages, 10 figures. For the Nobel Symposium on Qubits for Quantum Information, submitted to Physica Scripta. v. 2 Corrections and small changes to reference